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1 of 31 rev: 121903 general description the DS21Q55DK is an easy-to-use evaluation board for the ds21q55 quad t1/e1/j1 transceiver. the DS21Q55DK is intended to be used as a daughter card with the dk101 motherboard or the dk2000 motherboard. the DS21Q55DK comes complete with a ds21q55 quad sct, transformers, termination resistors, configuration switches, line-protection circuitry, network connectors, and motherboard connectors. the dk101/dk2000 motherboard and dallas? chipview software give point-and-click access to configuration and status registers from a windows -based pc. on-board leds indicate receive loss-of-signal and interrupt status. an on- board fpga contains mux logic to connect framer ports to one another or to the dk2000 in a variety of configurations. each DS21Q55DK is shipped with a free dk101 motherboard. for complex applications, the dk2000 high-performance demo kit motherboard can be purchased separately. windows is a registered trademark of microsoft corp. ordering information part description DS21Q55DK ds21q55 demo kit daughter card (with included dk101 motherboard) features demonstrates key functions of ds21q55 quad t1/e1/j1 transceiver includes ds21q55 quad liu, transformers, bnc, and rj45 network connectors and termination passives compatible with dk101 and dk2000 demo kit motherboards dk101/dk2000 and chipview software provide point-and-click access to the ds21q55 register set all equipment-side framer pins are easily accessible for external data source/sink memory-mapped fpga provides flexible clock/data/sync connections among framer ports and dk2000 motherboard leds for loss-of-signal and interrupt status easy-to-read silk-screen labels identify the signals associated with all connectors, jumpers and leds network interface protection for overvoltage and overcurrent events design kit contents DS21Q55DK design kit daughter card dk101 low-cost motherboard cd-rom chipview software DS21Q55DK data sheet dk101 data sheet ds21q55 data sheet ds21q55 errata sheet www.maxim-ic.com DS21Q55DK quad t1/e1/j1 transceiver design kit daughter card
DS21Q55DK quad t1/e1/j1 transceiver design kit 2 of 31 component list designation qty descri ption supplier part c1?c8 8 0.22 f, 50v capacitors phycomp pcf1150ct-nd c9, c10, c12, c18, c22?c33, c35, c38?c43 23 0.1 f 10%, 16v ceramic capacitors (0603) phycomp 06032r104k7b20d c11, c13?c15 4 0.1 f 10%, 25v ceramic capacitors (1206) panasonic ecj-3vb1e104k c16, c17, c19?c21, c34, c36, c45 8 1 f 10%, 16v ceramic capacitors (1206) panasonic ecj-3yb1c105k c37, c44 2 10 f 20%, 10v ceramic capacitors (1206) panasonic ecj-3yb1a106m ch1 1 quad port choke pulse tx1473 ds1 1 led, red, smd panasonic ln1251c ds2?ds6 5 led, green, smd panasonic ln1351c f1?f16 16 1.25a, 250v fuse, smt teccor f1250t j1 1 10-pin, dual row, vertical jumper digi-key s2012-05-nd j2?j9 8 5-pin connectors, bnc right-angle vertical cambridge cp-bncpc-004 j10 1 8-pin 4-port jack, right-angle rj45 molex 43223-8140 j11, j12 2 50-pin socket, smd, dual row, vertical samtec tfm-125-02-s-d-lc j13 1 12-pin connector, dual row, vertical digi-key s2012-06-nd r1, r2, r4 3 10k 1%, 1/10w resistors (0805) panasonic erj-6enf1002v r3, r26, r39, r41, r45 5 10k 5%, 1/10w resistors (0805) panasonic erj-6geyj103v r5?r12, r14?r21, r48 17 0 5%, 1/8w resistors (1206) panasonic erj-8geyj0r00v r13 1 470 5%, 1/10w resistor (0805) panasonic erj-6geyj471v r22?r25 4 51.1 1%, 1/10w resistors (0805) panasonic erj-6enf51r1v r27, r28, r38 3 1.0k 1%, 1/10w resistors (0805) panasonic erj-6enf1001v r29?r36 8 61.9 1%, 1/8w resistors (1206) panasonic erj-8enf61r9v r37, r47 2 not populated panasonic not populated r40, r42?r44, r46, r49 6 330 0.1%, 1/10w mf resistors (0805) panasonic era-6yeb331v sw1?sw4 4 6-pin th switch dpdt tyco ssa22 t1 1 xfmr, xmit/rcv, 1 to 2, smt 32-pin pulse tx1473 u1 1 xilinx spartan 2.5v fpga 144-pin, 20 x 20 tqfp xilinx xc2s50-5tq144c u2 1 quad t1/e1/j1 transceiver 256-pin bga, 0c to +70c multichip module dallas semiconductor ds21q55 u3 1 1m prom for fpga 44-pin tqfp xilinx xc18v01vq44c_u u4 1 8-pin max, so 2.5v or adj maxim max1792eua25 u20 1 serial configuration eeprom for xilinx 65kb, 8-dip atmel at17lv65eua-nopop z1?z8 8 50a, 6v sidactor, do214 smd teccor p0080samc z9?z16 8 500a, 25v sidactor, do214 smd teccor p0300scmc z17?z32 16 500a, 170v sidactor, do214 smd teccor p1800scmc
DS21Q55DK quad t1/e1/j1 transceiver design kit 3 of 31 board floorplan errata connector j1 has silk-screen mislabeled such that the text tms and tck should be swapped. worded differently, tck belongs to pin 7 and tms belongs to pin 9. switches sw1 to sw4 are missing silk screen to indicate which side is grounded. sliding the switch toward the bnc grounds the bnc shell (e1 mode). for t1 mode the switch should be slid away from the bnc. basic operation this design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/telecom . see the DS21Q55DK quickview data sheet for these files. hardware configuration using the dk101 processor board: connect the daughter card to the dk101 processor board. supply 3.3v to the banana-plug receptacles marked gnd and vcc_3.3v. (the external 5v connector is unused. additionally, the ?tim 5v supply? headers are unused.) all processor board dip-switch settings should be in the on position with exception of the flash-programming switch, which should be off. from the programs menu, launch the host application named chipview.exe. run the chipview application. if the default installation options were used, click the start button on the windows toolbar and select programs chipview chipview. using the dk2000 processor board: connect the daughter card to the dk2000 processor board. connect j1 to the power supply that is delivered with the kit. alternately, a pc power supply may be connected to connector j2. from the programs menu, launch the host application named chipview.exe. run the chipview application. if the default installation options were used, click the start button on the windows toolbar and select programs chipview chipview. rj45 x 4 bnc port 4 bnc port 3 bnc port 2 bnc port 1 line protection port 4 line protection port 3 line protection port 2 line protection port 1 ds21q55 fpga config prom cpu interface cpu interface fpga jtag pcm bus test points rlos 1-4 leds int led fpga status led quad port transformer quad port choke 2.5v fpga supply impedance matching/ line protection
DS21Q55DK quad t1/e1/j1 transceiver design kit 4 of 31 general upon power-up, the rlos leds (green) will not be lit, the int led (red) will not be lit, but the fpga status led (green) will be lit. when operating in e1 mode, slide sw1?sw4 such that the bnc shell is grounded (to the left, as shown in the board floorplan). when operating in t1 mode, ensure that sw1?sw4 are slid to the right as shown in the board floorplan. miscellaneous clock frequencies and certain pin bias levels are provided by a register-mapped fpga, which is on the ds21q55 daughter card. the definition file for this fpga is named ds21q55dc_fpga.def. the definitions are located on page 6. a drop-down menu on the top of the screen allows for switching between definition files. all files referenced above are available for download as described in the section marked ?basic operation ? quick setup (demo mode) the pc will load chipview offering a choice between demo mode, register view, and terminal mode. select demo mode. the program will request a configuration file, select among the displayed files (ds2155_e1_dsncom_drvr.cfg or ds2155_t1_dsncom_drvr.cfg). the demo mode screen will appear. upon external loopback, the los and oof indicators will extinguish. note: demo mode interacts with the device driver, which is resident in the dk101/dk2000 firmware. the current implementation of this driver is for one device. as such, the demo mode will only interact with port 1 . with minor changes, the device driver is extendible to n devices. quick setup (register view) the pc will load chipview offering a choice between demo mode, register view, and terminal mode. select register view. the program will request a definition file. select ds21q55dc_fpga.def; through the ?links? section this will also load ds21q55dc.def. the register view screen will appear, showing the register names, acronyms, and values for the ds21q55 predefined register settings for several functions are available as initialization files. ini files are loaded by selecting the menu f ile r eg ini file l oad ini file load the ini file ds21q55_t1_bert_esf.ini after loading the ini file, the following may be observed: the rlos leds (green) light upon external loopback. all four ports of the ds2q155 begin transmitting a daly pattern. when external loopback is applied, the bert bit count registers bbc1?3 and bec1?3 may be updated by clearing and setting bc1.lc and clicking the ?read all? button.
DS21Q55DK quad t1/e1/j1 transceiver design kit 5 of 31 address map dk101 daughter card address space begins at 0x81000000. dk2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 all offsets given below are relative to the beginning of the daughter card address space (shown above). table 1. daughter card address map offset device description 0x0000 to 0x0015 fpga board identification and clock/signal routing 0x1000 to 0x10ff t1/e1/j1 transceiver #1 ds21q55 t1/e1/j1 transceiver, port 1 0x2000 to 0x20ff t1/e1/j1 transceiver #2 ds21q55 t1/e1/j1 transceiver, port 2 0x3000 to 0x30ff t1/e1/j1 transceiver #3 ds21q55 t1/e1/j1 transceiver, port 3 0x4000 to 0x40ff t1/e1/j1 transceiver #4 ds21q55 t1/e1/j1 transceiver, port 4 registers in the fpga may be easily modified using the chipview host-based user-interface software along with the definition file named ?ds21q55dc_fpga.def.?
DS21Q55DK quad t1/e1/j1 transceiver design kit 6 of 31 fpga register map table 2. fpga register map offset register name type description 0x0000 bid read-only board id 0x0002 xbidh read-only high-nibble extended board id 0x0003 xbidm read-only middle-nibble extended board id 0x0004 xbidl read-only low-nibble extended board id 0x0005 brev read-only board fab revision 0x0006 arev read-only board assembly revision 0x0007 prev read-only pld revision 0x0011 mcsr control ds21q55 mclk pin source 0x0012 tcsr control ds21q55 tclk pin source 0x0013 sysclkt control ds21q55 tsysclk pin setting 0x0014 sysclkr control ds21q55 rsysclk pin setting 0x0015 sync1 control ds21q55 tsync source 0x0016 sync2 control ds21q55 tssync source 0x0017 sync3 control ds21q55 rsync source 0x0018 tsers control tser source 0x0019 prser control pcm rser source 0x001a psync control pcm rsync/tsync source 0x001b pclk control pcm rclk/tclk source id registers bid: board id (offset=0x0000) bid is read only with a value of 0xd xbidh: high nibble extended board id (offset=0x0002) xbidh is read only with a value of 0x0 xbidm: middle nibble extended board id (offset=0x0003) xbidm is read only with a value of 0x1 xbidl: low nibble extended board id (offset=0x0004) xbidl is read only with a value of 0x6 brev: board fab revision (offset=0x0005) brev is read only and displays the current fab revision arev: board assembly revision (offset=0x0006) arev is read only and displays the current assembly revision prev: pld revision (offset=0x0007) prev is read only and displays the current pld firmware revision
DS21Q55DK quad t1/e1/j1 transceiver design kit 7 of 31 control registers register name: mcsr register description: ds21q55 mclk pin source register offset: 0x0011 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? ? ? msrcb msrca default ? ? ? ? ? ? 1 1 bit 0: ds21q55 port 1 and 3 mclk source (msrca) 0 = connect mclk 1 (controls port 1 and 3) to the 1.544mhz clock 1 = connect mclk 1 (controls port 1 and 3) to the 2.048mhz clock bit 1: ds21q55 port 2 and 4 mclk source (msrca) 0 = connect mclk 2 (controls port 2 and 4) to the 1.544mhz clock 1 = connect mclk 2 (controls port 2 and 4) to the 2.048mhz clock register name: tcsr register description: ds21q55 tclk pin source register offset: 0x0012 bit # 7 6 5 4 3 2 1 0 name t4s1 t4s0 t3s1 t3s0 t2s1 t2s0 t1s1 t1s0 default 0 0 0 0 0 0 0 0 bit 0 to 1: ds21q55 port 1 tclk source (t1s0, t1s1) the source for tclk 1 is defined as shown in table 3. bit 2 to 3: ds21q55 port 2 tclk source (t2s0, t2s1) the source for tclk 2 is defined as shown in table 3. bit 4 to 5: ds21q55 port 3 tclk source (t3s0, t3s1) the source for tclk 3 is defined as shown in table 3. bit 6 to 7: ds21q55 port 4 tclk source (t4s0, t4s1) the source for tclk 3 is defined as shown in table 3. table 3. tclkx source definition txs1, txs0 tclk connection 00 drive tclk x with the 1.544mhz clock 01 drive tclk x with the 2.048mhz clock 10 drive tclk x with rclk x 11 n/a
DS21Q55DK quad t1/e1/j1 transceiver design kit 8 of 31 register name: sysclkt register description: ds21q55 tsysclk pin setting register offset: 0x0013 bit # 7 6 5 4 3 2 1 0 name r4s1 r4s0 r3s1 r3s0 r2s1 r2s0 r1s1 r1s0 default 0 0 0 0 0 0 0 0 bit 0 to 1: ds21q55 port 1 tsysclk source (r1s0, r1s1) the source for tsysclk 1 is defined as shown in table 4. bit 2 to 3: ds21q55 port 2 tsysclk source (r2s0, r2s1) the source for tsysclk 2 is defined as shown in table 4. bit 4 to 5: ds21q55 port 3 tsysclk source (r3s0, r3s1) the source for tsysclk 3 is defined as shown in table 4. bit 6 to 7: ds21q55 port 4 tsysclk source (r4s0, r4s1) the source for tsysclk 4 is defined as shown in table 4. table 4. tsysclkx source definition rxs1, rxs0 tsysclk x connection 00 drive tsysclk x with the 1.544mhz clock 01 drive tsysclk x with the 2.048mhz clock 10 drive tsysclk x with 8.192mhz clock 11 drive tsysclk x with ds21q55 port x bpclk register name: sysclkr register description: ds21q55 rsysclk pin setting register offset: 0x0014 bit # 7 6 5 4 3 2 1 0 name t4s1 t4s0 t3s1 t3s0 t2s1 t2s0 t1s1 t1s0 default 0 0 0 0 0 0 0 0 bit 0 to 1: ds21q55 port 1 rsysclk source (t1s0, t1s1) the source for rsysclk 1 is defined as shown in table 5. bit 2 to 3: ds21q55 port 2 rsysclk source (t2s0, t2s1) the source for rsysclk 2 is defined as shown in table 5. bit 4 to 5: ds21q55 port 3 rsysclk source (t3s0, t3s1) the source for rsysclk 3 is defined as shown in table 5. bit 6 to 7: ds21q55 port 4 rsysclk source (t4s0, t4s1) the source for rsysclk 4 is defined as shown in table 5. table 5. rsysclkx source definition txs1, txs0 rsysclk x connection 00 drive rsysclk x with the 1.544mhz clock 01 drive rsysclk x with the 2.048mhz clock 10 drive rsysclk x with 8.192mhz clock 11 drive rsysclk x with ds21q55 port x bpclk
DS21Q55DK quad t1/e1/j1 transceiver design kit 9 of 31 register name: sync1 register description: ds21q55 tsync pin source register offset: 0x0015 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? t4src t3src t2src t1src default ? ? ? ? 0 0 0 0 bit 0: ds21q55 port 1 tsync source (t1src) 0 = tsync 1 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tsync 1 with rsync 1 bit 1: ds21q55 port 2 tsync source (t2src) 0 = tsync 2 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tsync 2 with rsync 2 bit 2: ds21q55 port 3 tsync source (t3src) 0 = tsync 3 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tsync 3 with rsync 3 bit 3: ds21q55 port 4 tsync source (t4src) 0 = tsync 4 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tsync 4 with rsync 4 note: when driving tsyncx with rsyncx the corresponding ds21q55 port should be configured such that tsyncx is an input (iocr1.1 = 0) and rsyncx is an output (iocr1.4 = 0). register name: sync2 register description: ds21q55 tssync pin source register offset: 0x0016 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? t4src t3src t2src t1src default ? ? ? ? 0 0 0 0 bit 0: ds21q55 port 1 tssync source (t1src) 0 = not using transmit-side elastic store, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tssync 1 with rsync 1 bit 1: ds21q55 port 2 tssync source (t2src) 0 = not using transmit-side elastic store, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tssync 2 with rsync 2 bit 2: ds21q55 port 3 tssync source (t3src) 0 = not using transmit-side elastic store, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tssync 3 with rsync 3 bit 3: ds21q55 port 4 tssync source (t4source) 0 = not using transmit-side elastic store, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive tssync 4 with rsync 4 note: when driving tssyncx with rsyncx the corresponding ds21q55 port should be configured such that rsyncx is an output (iocr1.4 = 0).
DS21Q55DK quad t1/e1/j1 transceiver design kit 10 of 31 register name: sync3 register description: ds21q55 rsync pin setting register offset: 0x0017 bit # 7 6 5 4 3 2 1 0 name rsor1 rsor0 ? ? r4 io r3io r2io r1io default 0 0 ? ? 0 0 0 0 bit 0: ds21q55 port 1 rsync setting (r1io) 0 = rsync 1 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive rsync 1 with rsync x as shown in table 6 bit 1: ds21q55 port 2 rsync setting (r2io) 0 = rsync 2 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive rsync 2 with rsync x as shown in table 6 bit 2: ds21q55 port 3 rsync setting (r3io) 0 = rsync 3 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive rsync 4 with rsync x as shown in table 6 bit 3: ds21q55 port 4 rsync setting (r4io) 0 = rsync 4 is an output, tri-state corresponding fpga driver pin (weak pulldown) 1 = drive rsync 4 with rsync x as shown in table 6 note: when driving rsyncy with rsyncx the corresponding ds21q55 port should be configured such that rsyncx is an output (iocr1.4 = 0) and rsyncy is an input (iocr1.4 = 1). table 6. rsyncx function definition rsor1, rsor0 master rsync designation 00 rsync 1 is used to drive other rsync pins (providing r x io = 1) 01 rsync 2 is used to drive other rsync pins (providing r x io = 1) 10 rsync 3 is used to drive other rsync pins (providing r x io = 1) 11 rsync 4 is used to drive other rsync pins (providing r x io = 1) register name: tsers register description: ds21q55 tser pin source register offset: 0x0018 bit # 7 6 5 4 3 2 1 0 name t4s1 t4s0 t3s1 t3s0 t2s1 t2s0 t1s1 t1s0 default 0 0 0 0 0 0 0 0 bit 0 to 1: ds21q55 port 1 tser source (t1s0, t1s1) the source for tser 1 is defined as shown in table 4. bit 2 to 3: ds21q55 port 2 tser source (t2s0, t2s1) the source for tser 2 is defined as shown in table 4. bit 4 to 5: ds21q55 port 3 tser source (t3s0, t3s1) the source for tser 3 is defined as shown in table 4. bit 6 to 7: ds21q55 port 4 tser source (t4s0, t4s1) the source for tser 4 is defined as shown in table 4.
DS21Q55DK quad t1/e1/j1 transceiver design kit 11 of 31 table 7. tserx source definition txs1, txs0 tser x connection 00 tri-state tser x (weak pulldown) 01 drive tser x with rser x 10 drive tser x with pcm_txd bus (dk2000 only) 11 n/a register name: prser register description: pcm rser source register offset: 0x0019 bit # 7 6 5 4 3 2 1 0 name ? ? ? ? r1en r1en r1en r1en default ? ? ? ? 0 0 0 0 bit 0 to 1: pcm rser source (r1en) 0 = do not drive ds21q55 port 1 rser onto pcm_rser 1 = logically or ds21q55 port 1 rser with selected other rser pins and drive onto pcm_rser bit 2 to 3: ds21q55 port 2 tser source (t2s0, t2s1) 0 = do not drive ds21q55 port 2 rser onto pcm_rser 1 = logically or ds21q55 port 2 rser with selected other rser pins and drive onto pcm_rser bit 4 to 5: ds21q55 port 3 tser source (t3s0, t3s1) 0 = do not drive ds21q55 port 3 rser onto pcm_rser 1 = logically or ds21q55 port 3 rser with selected other rser pins and drive onto pcm_rser bit 6 to 7: ds21q55 port 4 tser source (t4s0, t4s1) 0 = do not drive ds21q55 port 4 rser onto pcm_rser 1 = logically or ds21q55 port 4 rser with selected other rser pins and drive onto pcm_rser note: prser register is for use with the dk2000 only.
DS21Q55DK quad t1/e1/j1 transceiver design kit 12 of 31 register name: psync register description: pcm rsync/tsync source register offset: 0x001a bit # 7 6 5 4 3 2 1 0 name ? ? t2sr t1sr ? ? r2sr r1sr default ? ? 0 0 ? ? 0 0 bit 0 to 1: pcm_rsync source r2sr, r1sr pcm_rsync source 00 pcm_rsync is driven by ds21q55 port 1 rsync. 01 pcm_rsync is driven by ds21q55 port 2 rsync. 10 pcm_rsync is driven by ds21q55 port 3 rsync. 11 pcm_rsync is driven by ds21q55 port 4 rsync. bit 4 to 5: pcm_tsync source t2sr, t1sr pcm_tsync source 00 pcm_tsync is driven by ds21q55 port 1 tsync. 01 pcm_tsync is driven by ds21q55 port 2 tsync. 10 pcm_tsync is driven by ds21q55 port 3 tsync. 11 pcm_tsync is driven by ds21q55 port 4 tsync. note: psync register is for use with the dk2000 only.
DS21Q55DK quad t1/e1/j1 transceiver design kit 13 of 31 register name: pclk register description: pcm rclk/tclk source register offset: 0x001b bit # 7 6 5 4 3 2 1 0 name ? tcm t2sr t1sr ? rcm r2sr r1sr default ? 0 0 0 ? 0 0 0 bit 0 to 2: pcm_rclk source rcm, r2sr, r1sr pcm_rclk source 000 pcm_rclk is driven by ds21q55 port 1 rclk. 001 pcm_rclk is driven by ds21q55 port 2 rclk. 010 pcm_rclk is driven by ds21q55 port 3 rclk. 011 pcm_rclk is driven by ds21q55 port 4 rclk. 100 pcm_rclk is driven by ds21q55 port 1 bpclk. 101 pcm_rclk is driven by ds21q55 port 2 bpclk. 110 pcm_rclk is driven by ds21q55 port 3 bpclk. 111 pcm_rclk is driven by ds21q55 port 4 bpclk. bit 4 to 5: pcm_tclk source tcm, t2sr, t1sr pcm_tclk source 000 pcm_tclk is driven by source used for ds21q55 port 1 tclk. 001 pcm_tclk is driven by source used for ds21q55 port 2 tclk. 010 pcm_tclk is driven by source used for ds21q55 port 3 tclk. 011 pcm_tclk is driven by source used for ds21q55 port 4 tclk. 100 pcm_tclk is driven by ds21q55 port 1 bpclk. 101 pcm_tclk is driven by ds21q55 port 2 bpclk. 110 pcm_tclk is driven by ds21q55 port 3 bpclk. 111 pcm_tclk is driven by ds21q55 port 4 bpclk. note: pclk register is for use with the dk2000 only.
DS21Q55DK quad t1/e1/j1 transceiver design kit 14 of 31 fpga control examples table 8. fpga configuration for scenario #1 (port 1, t1 mode) register setting function mcsr 0x01 drive ds21q55 ports 1 and 3 mclk with 2.048mhz tcsr 0x00 drive tclk with 1.544mhz sysclkt 0x00 drive tsysclk with 1.544mhz sysclkr 0x00 drive rsysclk with 1.544mhz sync1 0x00 tri-state fpga driver pin for ds21q55 tsync1 sync2 0x01 drive tssync1 with rsync1 sync3 0x00 tri-state fpga driver pin for ds21q55 rsync tsers 0x02 drive ds21q55 tser1 with data from pcm bus prser 0x01 drive ds21q55 rser1 onto pcm bus psync 0x00 pcm rsync and pcm tsync are provided by ds21q55 port 1 rsync and tsync (respectively) pclk 0x44 pcm rclk and tclk are driven by port 1 bpclk tser tclk bpclk tsync rser rclk bpclk rsync ds21q55 pcm_txd pcm_tclk pcm_tsync pcm_rxd pcm_rclk pcm_rsync dk2000 xo scenario #1: ds21q55 to/from dk2000
DS21Q55DK quad t1/e1/j1 transceiver design kit 15 of 31 table 9. fpga configuration for scenario #2 (port 1, t1 mode) register setting function mcsr 0x01 drive ds21q55 ports 1 and 3 mclk with 2.048mhz tcsr 0x02 drive tclk1 with rclk1 sysclkt 0x00 drive tsysclk with 1.544mhz sysclkr 0x00 drive rsysclk with 1.544mhz sync1 0x01 drive tsync1 with rsync1 sync2 0x01 drive tssync1 with rsync1 sync3 0x00 tri-state fpga driver pin for ds21q55 rsync tsers 0x01 drive ds21q55 tser1 with data from rser1 prser n/a unused psync n/a unused pclk n/a unused table 10. ds21q55 partial configuration for scenario #2 (port 1, t1 mode) register setting function iocr1 tsio = 0; rsio = 0 tsync is an input, rsync is an output escr tese = 0; rese = 0 bypass rx and tx elastic stores ccr1 tcss1 = 0; tcss2 = 0 tclk is driven by tclk pin scenario #2: external remote loopback ( full bandwidth , not just payload ) tser tclk bpclk tsync rser rclk bpclk rsync ds21q55
DS21Q55DK quad t1/e1/j1 transceiver design kit maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa 16 of 31 ds21q55 information for more information about the ds21q55, please consult the ds21q55 data sheet available on our website at www.maxm-ic.com/ds21q55 . software downloads are also available for this demo kit. DS21Q55DK information for more information about the DS21Q55DK, including software downloads, please consult the DS21Q55DK data sheet available on our website at www.maxim-ic.com/telecom . technical support for additional technical support, please e-mail your questions to telecom.support@dalsemi.com . schematics the DS21Q55DK schematics are featured in the following pages.

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